1. Field of the Invention
The present invention relates to a method for producing a ceramic substrate, and an electronic component module using a ceramic substrate produced by the production method. In particular, the present invention relates to a method for producing a ceramic substrate having convex portions (bumps) on a surface, and an electronic component module using a ceramic substrate produced by the production method.
2. Description of the Related Art
Hereinafter, a conventional method for producing a ceramic substrate with convex portions (bumps) will be described. FIG. 10 shows the processes of the conventional method for producing a ceramic substrate. More specifically, according to the conventional method, via holes are opened in a green sheet for sintering at low temperature (process 1). Thereafter, the via holes are filled with a conductor made of a silver paste (process 2). An inner layer conductor is formed on a surface layer of the green sheet filled with the conductor, whereby a plurality of green sheets with the inner layer conductors formed thereon are prepared (process 3). Separately from these processes, for pressing the green sheets, via holes are opened in a shrinkage suppressing layer made of an unbaked sheet that is not sintered at the sintering temperature of the green sheets (process 4), and the via holes formed in the process 4 are filled with a conductor (process 5). The green sheets formed in the process 3 are laminated, and the shrinkage suppressing layer filled with the conductor formed in the process 5 is laminated on an outermost layer of the laminate, followed by pressing (process 6). After the process 6, the resultant laminate is sintered at about 900° C. (process 7). After the process 7, the shrinkage suppressing layer laminated in the process 6 is removed (process 8). Consequently, a substrate with convex portions as shown in FIG. 11 is completed.
FIG. 11 shows a specific example of an electronic component module using a substrate with convex portions. Reference numeral 11 denotes a ceramic substrate in which a laminate of green sheets is sintered at low temperature, 12 denotes inner vias each connecting an upper surface to a lower surface of each layer of the ceramic substrate 11, and 13 denotes inner layer patterns. Reference numeral 14a denotes convex portions composed of a conductor formed on a lowermost layer 11b of the ceramic substrate 11, and 20 denotes a surface layer pattern connected to the convex portions 14a. Furthermore, reference numeral 15 denotes convex portions composed of a conductor formed on an uppermost layer 11a of the ceramic substrate 11, which is connected to a surface layer pattern 16 on the uppermost layer 11a and the inner vias 12.
Reference numeral 17 denotes a flip chip IC mounted on the upper surface of the ceramic substrate 11. A connection layer 18 formed on a bottom surface of the flip chip IC 17 is connected to the convex portions 15. Thus, an electronic component module 19 as a surface mounting module is completed. The prior art related to the invention of the present application is, for example, described in JP6 (1994)-53655A.
However, according to the conventional method for producing a ceramic substrate with convex portions, the shrinkage suppressing layer filled with a conductor is laminated on a green sheet laminate that has not been sintered, and thereafter, the shrinkage suppressing layer and the green sheet laminate are sintered simultaneously, whereby convex portions are formed. At this time, the green sheet laminate needs to be sintered, so that sintering is performed at a maximum temperature of 900° C. for a retention time of 20 minutes (JP6(1994)-53655A). In general, the baking temperature of a conductor, a dielectric (insulator), and a resistant material used as a thick film material is in a range of 850° C.±50° C., and the baking temperature at the center of a distribution is lower than about 900° C. that is the sintering temperature of the green sheet laminate. Thus, according to the conventional production method, only a conductive material that is baked at 900° C. can be used, and a general thick film material cannot be selected arbitrarily to form convex portions.
For example, the material for convex portions in JP6(1994)-53655A is limited to a conductive material containing no glass frit. However, the glass frit is largely related to the connection strength between the convex portions and the green sheets; therefore, when the convex portions are formed of a conductor containing no glass frit, convex portions with low connection strength with respect to the substrate or ceramic surface are likely to be formed. Thus, the convex portions formed by this method have low connection reliability.
Furthermore, according to the prior art, convex portions composed of a mixture of different kinds of thick film materials (i.e., convex portions in which a dielectric and a conductor are mixed) cannot be formed. Therefore, the following problem arises. There is a limit to a dimension 21 between the convex portions 14a and 14b including the surface layer pattern 20. That is, as shown in FIG. 12, when the electronic component module 19 is soldered to a parent substrate 22, if the dimension 21 is small, a short due to soldering occurs between the convex portions 14a and 14b including the surface layer pattern 20.
Herein, reference numeral 23a denotes lands formed on an upper surface of the parent substrate 22, and the lands 23a are provided at positions corresponding to the convex portions 14a. Similarly, reference numeral 23b denotes lands provided at positions corresponding to the convex portions 14b. 